Article ID: 000080671 Content Type: Troubleshooting Last Reviewed: 12/06/2024

Why is the last output frame of the FFT IP core missing EOP?

Environment

    Intel® Quartus® Prime Pro Edition
    FFT Intel® FPGA IP
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Due to a problem with the FFT IP core in Quartus® Prime Standard Software version 18.1, you may observe that the last output frame of the FFT IP core is missing EOP when both the Input Order and Output Order are configured to Natural and there are intervals with sink_valid = 0 between input frames.

Resolution

Configure the Output Order in FFT IP to be Digit Reverse.

 

Related Products

This article applies to 11 products

Cyclone® IV FPGAs
Stratix® V FPGAs
Intel® Stratix® 10 FPGAs and SoC FPGAs
Cyclone® V FPGAs and SoC FPGAs
Intel® Cyclone® 10 FPGAs
Intel® Arria® 10 FPGAs and SoC FPGAs
Arria® V FPGAs and SoC FPGAs
Stratix® IV FPGAs
Arria® II GX FPGA
Arria® II GZ FPGA
Intel® MAX® 10 FPGAs

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