Article ID: 000080665 Content Type: Product Information & Documentation Last Reviewed: 03/21/2019

How do I provide the Advance Interface Bus (AIB) clock to the E-tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP using an IOPLL or a Native PHY in PLL Mode?

Environment

  • Intel® Stratix® 10 FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • E-tile Hard IP for Ethernet Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    Due to a restriction in the current release of the E-tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP, external clock source cannot be used as an input to provide to the AIB clock.

    Resolution

    This capability is scheduled to be added to a future release of the Intel® Quartus® Prime software.

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