Article ID: 000080659 Content Type: Troubleshooting Last Reviewed: 02/08/2017

Why does the Low Latency 40-100Gbps Ethernet IP core indicate payload length error for RX frames with payload size less than 46 bytes?

Environment

    Intel® Quartus® Prime Standard Edition
    Intel® Quartus® Prime Pro Edition
    Quartus® II Subscription Edition
    Low Latency 40G 100G Ethernet
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Description

The Low Latency 40-100Gbps Ethernet IP core incorrectly interprets any value in the length field of a packet with payload size less than 46 bytes as an error. This issue occurs because the IP core does not adequately allow for the case in which the Ethernet link partner padded a short payload with padding bytes as required by the Ethernet protocol.

 

Example:

Actual payload = 17 bytes

Minimum payload size = 17 bytes 29 bytes padded zeros = 46 bytes

Length field = 17 bytes

17 bytes < 46 bytes, which causes the IP core to report incorrect payload length error

Resolution

The problem will be addressed in a future version of the Low Latency 40-100 Gbps Ethernet IP core.

Related Products

This article applies to 7 products

Intel® Arria® 10 FPGAs and SoC FPGAs
Intel® Arria® 10 GT FPGA
Intel® Arria® 10 GX FPGA
Intel® Arria® 10 SX SoC FPGA
Stratix® V E FPGA
Stratix® V GS FPGA
Stratix® V GX FPGA

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