Description
Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 17.1 and earlier, you may see this error message when compiling a design that includes the LVDS IP.
This problem occurs when the IP is in external PLL mode and targets an Intel Stratix® 10 device.
Resolution
To work around this problem, comment out the following line from the LVDS IP SDC file
set_max_delay_in_fit_or_false_path_in_sta_through_no_warn ${pll_instance_name}|lock $max_delay
This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.