Description
In the Platform Designer Component Editor, you may see this error when running Analyse Synthesis Files and your file has inputs or outputs with VHDL types such as bit, std_ulogic or a custom type.
Resolution
To avoid this error, either use std_logic or std_logic_vector types for your ports or manually enter the interface signals.
This error is scheduled to be clarified in a future release of the Quartus® Prime Pro Edition Software.