Error: Verilog HDL or VHDL error at <design>.v object declared in a List of Port Declarations cannot be redeclared within the Module Body.

This error occurs in Verilog HDL designs when you use the Verilog-2001 port declaration style that defines the port type and width and then redeclare the reg data type in the module body.

Beginning with the Quartus^® II software version 5.0, the compiler includes Verilog-2001 checks that were not enforced in earlier versions. To resolve this problem, remove the declaration in the module body. Ports must be completely specified in the Verilog 2001 list of ports declaration, including where necessary the direction, width, net or variable type, and whether the port is signed or unsigned. Alternately, use the Verilog-1995 style of port declarations that defines just the port name and requires a separate line to define the port type and width.

For example, you can use this Verilog-2001 port declaration style:

module module_name (

   input reg[63:0] input_port_name, 

   output reg output_port_name,

   ...

);

Alternately, you can use this Verilog-1995 port declaration style:

module module_name (

   input_port_name, 

   output_port_name,

   ...

);

input reg[63:0] input_port_name, 

output reg output_port_name,

...