Due to a problem in the Quartus® II software, Quartus II synthesis may generate this error when trying to evaluate an indexed expression in VHDL that is outside the range within an if expression inside a loop.
You may see this error when all of the following conditions are met:
- An if statement is within a for loop
- The if statement is a comparison of two integer expressions using <, <=, >, >= or =
- The loop variable occurs in the expressions evaluated by the if statement
- The expression evaluated by the if statement is limited to , -, and *
Here is an example of when this error would occur:
entity test is
port
(
i1_data_in : in std_logic_vector(3 downto 0);
i_div_pos : in std_logic_vector(7 downto 0);
o_data_out : out std_logic_vector(7 downto 0)
);
END entity test;
architecture rtl of test is
signal idx : integer;
signal lim : NATURAL range 0 to 5;
idx <= to_integer(unsigned(i_div_pos));
lim <= 3;
process(i1_data_in, idx)
variable temp : std_logic_vector(o_data_out\'range);
begin
temp := (others => \'0\');
u1 : for i in 0 to 7 loop
if i <= 3 - lim then
temp(i) := i1_data_in(i);
else
temp(i) := i_div_pos (i);
end if;
end loop;
o_data_out <= temp;
end process;
end rtl;
A patch is available to fix this problem for the Quartus II software version 11.0 SP1. Download and install Patch 1.40 from the appropriate link below. After installing the patch, activate the fix by creating or editing the file quartus.ini in your project directory to include the following line:
vrfx_optimize_if_dead_code=on
- Download the version 11.0 SP1 patch 1.40 for Windows (.exe)
- Download the version 11.0 SP1 patch 1.40 for Linux (.tar)
- Download the Readme for the Quartus II software version 11.0 SP1 patch 1.40 (.txt)
If you encounter this error while using a different version of the Quartus II software, file a Service Request using mySupport.