Why does my VHDL design fail in hardware when I have a ‘range definition in a loop?

Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 20.3, you may see hardware failures when you have VHDL code in your design that uses a ‘range definition inside a generate loop that is declared inside a generate block, such as the code below. If your design is affected by this problem, your design will likely cause synthesis warnings messages such as the following:

Warning (16788): Net does not have a driver at .vhd(line number)

gen_example: case NUM generate
   when 8 =>  
      signal sig : std_logic_vector(1 downto 0);
      begin
         gen_test : for i in sig'range
         generate
            and_gate:and01    
            port map ( inp => inp, outp => outp);
         end generate gen_test;   
      end;
   end generate gen_example;

To work around this problem, download and install the Patch from the appropriate link below. 

• Download patch Intel® Quartus® Prime 20.3 Patch 0.02 for Windows (.exe)  
• Download patch Intel® Quartus® Prime 20.3 Patch 0.02  for Linux (.run)
• Download the Readme for Intel® Quartus® Prime 20.3 Patch 0.02 (.txt)

This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 20.4.