Due to a problem in the Intel® Quartus® Prime Pro Edition software version 19.3 and earlier, you may see the synthesis error messages below when you migrate a design that contains two or more DSP blocks from an Intel® Stratix® 10 device to an Intel Agilex® 7 device. This error only happens in VHDL but not Verilog HDL.
Error(17900): To properly enable the chainadder feature, port CHAININ for DSP block WYSIWYG primitive "<design_path>|<design_name>_DSP0" must be connected from the CHAINOUT port of the previous DSP block.
Error(17860): The width of port CHAININ for DSP block WYSIWYG primitive "|<design_name>_DSP0" should be 64 bits when parameter use_chainadder is set to "true."
The synthesis interprets the chain out width of the DSP blocks incorrectly as 0. You may need to change it accordingly based on your design requirement.
To work around this problem, you may double-click on the synthesis error message and manually modify the DSP block by adding the CHAINOUT port width for the Intel Agilex® device.
Refer to the following code example:
<design name>
GENERIC MAP (
operation_mode => "m27x27",
clear_type => "sclr",
...
chain_inout_width => <based on your design value>, // Add this code
output_clken => "1"
)
PORT MAP (
clk => clk,
...
chainout => ... // make sure this port is here before adding the above code
);
This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.3.