Article ID: 000080498 Content Type: Troubleshooting Last Reviewed: 10/12/2020

Why is the byte enable signal disconnected when generating 2-Port RAM IP core for Intel® Stratix® 10 devices?

Environment

  • Intel® Quartus® Prime Pro Edition
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    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition software version 20.2, you may see the byte enable signal is not connected to 2-Port RAM IP core for Intel® Stratix® 10 devices

    Resolution

    This problem has been fixed beginning with version 20.3 of the Intel® Quartus® Prime Pro Edition software.

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs

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