Why does Timing Analyzer not show RSKM value for external PLL LVDS Serdes FPGA IP?

Due to a problem in the Quartus® Prime Pro Edition software version 18.1 and earlier, Timing Analyzer will not show the RSKM value whenever external PLL RX LVDS Serdes FPGA IP has been used in your design. This problem occurs when the PLL RX LVDS Serdes FPGA IP is instantiated in a generate statement.

To work around this problem,

• Remove the -nowarn from line 400 sdc_util.tcl in <project_directory>\ip\ed_synth\<project_name>\altera_lvds_core20_<version>\synth.
• Avoid using “generate” statement for the LVDS Serdes FPGA IP instantiation in the verilog/vhdl code.

This problem is fixed starting with the Quartus® Prime Pro Edition Software version 19.1.