Why do the ports on a block in my DSP Builder for Intel® FPGAs design not redraw correctly after the port count is changed?

Due to a problem in DSP Builder for Intel® FPGAs version 19.1 and earlier in combination with Mathworks* Matlab* version R2018b and later, you may see that the mask appearance and displayed ports do not redraw correctly.

This occurs on blocks with variable numbers of input and/or output ports when the port counts are changed. The number of displayed ports does not change and the text "???" is rendered over part of the block image.

To work around this problem, perform any of the following steps:

• Save, close, and reopen the design.
• Perform type propagation (CTRL-D). The erroneous text "???" will still be shown, but the port counts will be correctly updated.
• Use Mathworks Matlab version R2018a or earlier.

This problem is scheduled to be fixed in a future release of DSP Builder for Intel FPGAs.