Article ID: 000080460 Content Type: Troubleshooting Last Reviewed: 05/13/2019

Why are there minimum pulse width timing violations in Fault Injection IP for Cyclone® V device with the Quartus® II software version 15.0 Update 2 ?

Environment

  • Quartus® II Subscription Edition
  • Fault Injection Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Quartus® II software version 15.0 Update 2, when the Single Event Upset(SEU) feature is implemented in the Cyclone® V device with the following clock constraint, you may find minimum pulse width timing violations for some signals in Fault Injection IP.

        create_clock -name intosc -period 10.000 [get_nets {*fault_injection_0|alt_fault_injection_component|alt_fi_inst|intosc}]

    Resolution

    The problem is fixed beginning with the Intel® Quartus® Prime Standard Edition software version 16.0r.

    Related Products

    This article applies to 1 products

    Cyclone® V FPGAs and SoC FPGAs

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