'!isROM'. attempt to create uninitialised read-only memory in CDualMem::GenHDL at p4/ip/aion/src/mip_common/hw_dualmem.cpp:1900

Due to a problem in DSP Builder for FPGAs version 18.1 Update 2 and earlier, you may see this error when your design contains any HDL Import subsystems. Subsystems are processed alphabetically: the error occurs when an HDL Import subsystem is, alphabetically, the last subsystem in the design.

To work around this problem, create a scheduled subsystem with no intenal hierarchy and a name that comes later alphabetically than the HDL Import subsystem. It is important that the workaround subsystem has no internal hierarchy because subsystems with internal hierarchy are renamed when the system hierarchy is flattened.

This problem is scheduled to be fixed in a future release of DSP Builder for Intel® FPGAs.