Article ID: 000080451 Content Type: Troubleshooting Last Reviewed: 02/14/2019

Why does the PLL simulation fail with Verilog HDL simulation model for Intel® Cyclone® 10 LP device?

Environment

  • Intel® Quartus® Prime Standard Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    The Verilog HDL simulation model for IOPLL IP for Intel® Cyclone® 10 LP devices is not supported in the Intel® Quartus® Prime Standard Edition software version 17.1 and earlier. You will see that the IOPLL output clocks do not toggle.

    Resolution

    To simulate the IOPLL IP for Intel® Cyclone® LP devices, either use the VHDL simulation model in 17.1 or the Verilog HDL model in the Intel® Quartus® Prime Standard Edition software version 18.0 or later.

    Related Products

    This article applies to 1 products

    Intel® Cyclone® 10 LP FPGA

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