Article ID: 000080438 Content Type: Troubleshooting Last Reviewed: 08/07/2019

Why does Intel® Quartus® Prime Standard/Pro software fail to pack coefficients into DSP Block when using FIR II IP core?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Intel® Quartus® Prime Standard Edition
  • FIR II Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime Standard/Pro Edition software version 17.1/18.0 and Intel® Quartus® Prime Standard Edition software version 18.1, the synthesis may not infer the use of DSP coefficients ROM correctly if you set AUTO_RAM_RECOGNITION and AUTO_ROM_RECOGNITION OFF. This results in low Fmax of FIR II IP core.

    Resolution

    To work around this problem in the Intel® Quartus® Prime Standard Edition software, follow the steps below. 

    Set Assignments > settings > compiler settings > Advanced settings(Synthesis) > Auto RAM Replacement from OFF to ON.

    Set Assignments > settings > compiler settings > Advanced settings(Synthesis) > Auto ROM Replacement from OFF to ON.

    This Problem has been fixed in  Intel® Quartus® Prime Pro Edition software version 18.1.

    Related Products

    This article applies to 1 products

    Intel® Arria® 10 FPGAs and SoC FPGAs

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