Article ID: 000080437 Content Type: Troubleshooting Last Reviewed: 01/17/2023

Why do I see a disparity error in my JESD204B receiver device when using the JESD204B Intel® FPGA IP in TX mode in Intel® Stratix® 10 devices with E-Tile transceivers?

Environment

  • Intel® Quartus® Prime Pro Edition
  • JESD204B Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 19.1, when using the JESD204B Intel® FPGA IP in TX mode in Intel® Stratix® 10 devices with E-Tile transceivers, the intellectual property (IP) will introduce a disparity error when configured for a single lane ( L=1) in bonded mode.

    Resolution

    To work around this problem, when configuring the JESD204B Intel® FPGA IP IP in L=1 mode, enable the non-bonded mode. 

    This problem is fixed strating from Intel® Quartus® Prime Pro Edition Software version 19.3.

    Related Products

    This article applies to 2 products

    Intel® Stratix® 10 TX FPGA
    Intel® Stratix® 10 MX FPGA

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