Why does the 25G Ethernet Intel® FPGA IP transmit incorrect traffic when either TX start of packet (SOP) or end of packet (EOP) are asserted on the same cycle the valid signal was de-asserted?

Due to a problem with the Intel® Quartus® Prime Pro Edition Software version 19.1 software, the 25G Ethernet Intel® FPGA IP with ready latency set to 3 will transmit incorrect traffic when either the TX start of packet (SOP) or end of packet (EOP) signals are asserted on the same cycle as the valid signal was de-asserted.

To work around this problem, only assert TX start of packet (SOP) or end of packet (EOP) when the valid signal is asserted.

This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 19.3.