Article ID: 000080433 Content Type: Troubleshooting Last Reviewed: 07/08/2019

Why does the 25G Ethernet Intel® FPGA IP transmit incorrect traffic when either TX start of packet (SOP) or end of packet (EOP) are asserted on the same cycle the valid signal was de-asserted?

Environment

  • Intel® Arria® 10 FPGAs and SoC FPGAs
  • Intel® Stratix® 10 FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • 25G Ethernet Intel® FPGA IP
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    Critical Issue

    Description

    Due to a problem with the Intel® Quartus® Prime Pro Edition version 19.1 software, the 25G Ethernet Intel® FPGA IP with ready latency set to 3 will transmit incorrect traffic when either the TX start of packet (SOP) or end of packet (EOP) signals are asserted on the same cycle as the valid signal was de-asserted.

    Resolution

    To work around this problem, only assert TX start of packet (SOP) or end of packet (EOP) when the valid signal is asserted.

    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.

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