Article ID: 000080432 Content Type: Troubleshooting Last Reviewed: 09/10/2019

Why does programming the csr_sysref_singledet register bit to '1' when the JESD204B Intel® FPGA IP is in ILAS phase bring the IP back to CGS state?

Environment

    Intel® Quartus® Prime Pro Edition
    Intel® Quartus® Prime Standard Edition
    JESD204B Intel® FPGA IP
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Due to a known problem in the Intel® Quartus® Prime Standard and Pro Edition Software, programming the csr_sysref_singledet register bit to '1' when the JESD204B Intel FPGA IP is in ILAS phase will bring the IP back to CGS state. This impacts Intel Agilex®, Intel Stratix® 10, Intel Arria® 10 and Intel Cyclone® 10 GX device families.To work around this problem, avoid programming the csr_sysref_singledet register bit when the JESD204B Intel FPGA IP is in ILAS phase. 

Resolution

To work around this problem, avoid programming the csr_sysref_singledet register bit when the JESD204B Intel FPGA IP is in ILAS phase. There is no fix planned for this. 

Related Products

This article applies to 4 products

Intel® Cyclone® 10 GX FPGA
Intel Agilex® 7 FPGAs and SoC FPGAs
Intel® Arria® 10 FPGAs and SoC FPGAs
Intel® Stratix® 10 FPGAs and SoC FPGAs

1

Need more help?

Contact support

Disclaimer

1

All postings and use of the content on this site are subject to Intel.com Terms of Use.