The Link Equalization Request bit (bit 5 of the Link Status 2 register) is set during PCIe* Gen3 link equalization. Once set, this bit cannot be cleared by software. The autonomous equalization mechanism is not affected by this issue, but the software equalization mechanism may be impacted depending on the usage of the Link Equalization Request bit.
Avoid using software based link equalization mechanism for both PCIe* endpoint and root port implementations, instead utilize the autonomous equalization mechanism. This problem is not scheduled to be fixed in any future releases of the Intel® Quartus® Prime Pro Edition software.