Article ID: 000080428 Content Type: Troubleshooting Last Reviewed: 05/05/2021

Why can't the Link Equalization Request bit be cleared by software when using the Intel® Arria® 10 Hard IP for PCIe* IP operating in Root Port mode?

Environment

  • Intel® Arria® 10 FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • Intel® Arria® 10 Cyclone® 10 Hard IP for PCI Express
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    Critical Issue

    Description

    The Link Equalization Request bit (bit 5 of the Link Status 2 register) is set during PCIe* Gen3 link equalization. Once set, this bit cannot be cleared by software. The autonomous equalization mechanism is not affected by this issue, but the software equalization mechanism may be impacted depending on the usage of the Link Equalization Request bit.

    Resolution

    Avoid using software based link equalization mechanism for both PCIe* endpoint and root port implementations, instead utilize the autonomous equalization mechanism. This problem is not scheduled to be fixed in any future releases of the Intel® Quartus® Prime Pro Edition software.

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