Article ID: 000080427 Content Type: Troubleshooting Last Reviewed: 01/25/2019

Why do I get “Overwriting previous definition” warnings when instantiating multiple instances of IPs.

Environment

  • Intel® Stratix® 10 GX FPGA
  • Intel® Stratix® 10 MX FPGA
  • Intel® Stratix® 10 TX FPGA
  • Intel® Stratix® 10 SX SoC FPGA
  • Intel® Quartus® Prime Pro Edition
  • 25G Ethernet Intel® FPGA IP
  • Ethernet
  • Low Latency 100G Ethernet Intel® FPGA IP for Arria® 10 and Stratix® V
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    Description

    Due to a problem in the Intel® Quartus® Prime software version, 18.1 and earlier, instantiating multiple instances of these IPs might cause fitter warnings of the following format: “Overwriting the previous definition of xyz module”. When the IP has different configurations, this could impact the functionality of the IP.

    Low Latency 100G Ethernet Intel® Stratix® 10 FPGA IP, 25G Ethernet Intel® Stratix® 10 FPGA IP, H-Tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP and E-Tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP

    Resolution

    This problem has been fixed starting in the Intel® Quartus® Prime revision v18.1.1.

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