Why is rx_pcs_ready unstable after linkup when using the Low Latency 100G Ethernet Intel® Stratix® 10 FPGA IP core?

Due to a problem with the Low Latency 100G Ethernet Intel® Stratix® 10 FPGA IP core rx_pcs_ready may be unstable following linkup.

This is caused by a problem with the reset release sequence, the PHY may not be stable causing the PCS ready to de-assert and cause some packets to be dropped during traffic.

To work around this problem when using the Intel® Quartus® Prime Software version 18.0 and earlier, ignore any glitch on rx_pcs_ready after reset.

This problem has been fixed starting in version 18.0.1 of the Intel® Quartus® Prime Software.