Article ID: 000080422 Content Type: Troubleshooting Last Reviewed: 07/08/2019

Why does the H-tile Hard IP for Ethernet Intel® FPGA IP Core failed to generate the design example?

Environment

  • Intel® Stratix® 10 FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • H-tile Hard IP for Ethernet Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition software version 19.2, the H-tile Hard IP for Ethernet Intel® FPGA IP Core will fail to generate a design example if the Target Development Kit is set to NONE.

    Resolution

    To work around this problem in the Intel® Quartus® Prime Pro Edition software version 19.2, set the Target Development Kit, to the kit featuring the device that closest matches the device in you own project.

    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition software.

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