Article ID: 000080422 Content Type: Troubleshooting Last Reviewed: 12/30/2022

Why does the H-tile Hard IP for Ethernet Intel® FPGA IP Core failed to generate the design example?

Environment

  • Intel® Quartus® Prime Pro Edition
  • H-tile Hard IP for Ethernet Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 19.2, the H-tile Hard IP for Ethernet Intel® FPGA IP Core will fail to generate a design example if the Target Development Kit is set to NONE.

    Resolution

    To work around this problem in the Intel® Quartus® Prime Pro Edition Software version 19.2, set the Target Development Kit to the kit featuring the device closest to your project's device.

    This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 19.3.

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs

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