Article ID: 000080416 Content Type: Troubleshooting Last Reviewed: 06/19/2019

Why does configuration fail with error message (18950), (18948) and (20072) when using the Intel® Stratix® 10 E-tile Hard IP for Ethernet Intel® FPGA IP compilation test design example?


  • Intel® Quartus® Prime Pro Edition
  • E-tile Hard IP for Ethernet Intel® FPGA IP

    FPGA configuration will fail with following error messages when using the compilation test design of the Intel® Stratix® 10 E-tile Hard IP for Ethernet Intel® FPGA IP example design targetting the Intel® Stratix® 10 TX Signal Integrity Development Kit:

    Error(18950): Device has stopped receiving configuration data 

    Error(18948): Error message received from device: Detected hardware access error. There is a failure in accessing external hardware. (Subcode 0x0032, Info 0x00000000, Location 0x0000B800) 

    Error(20072): A PMBUS error has occurred during configuration. Potential errors: Incorrect VID setting in Quartus Project. The target device fails to communicate to smart regulator or PMBUS Master on board. 

    Error(209012): Operation failed



    The compilation test design is intended for simulation and compilation only.

    To work around this problem and configure the compilation test design image to the development board change the Power Management & VID settings in Device and Pin Options of the project as below, or utilize the hardware test design:

    1. select Slave device type to Other

    2. set PMBus device 0 slave address to 47

    3. set PMBus device 1 slave address to 48



    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs



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