Article ID: 000080414 Content Type: Troubleshooting Last Reviewed: 04/29/2019

Why is the class code readout of the Intel® Arria® 10 Avalon®-ST Interface with SR-IOV PCIe* IP different from the class code value set in the IP GUI?

Environment

  • Intel® Arria® 10 FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • Intel® Arria® 10 Cyclone® 10 Hard IP for PCI Express
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    Description

    Unlike the regular Intel® Arria® 10 Avalon®-ST PCIe* IP variant, the Intel® Arria® 10 Avalon®-ST Interface with SR-IOV PCIe* IP variant has the 24-bit Class Code register split into three 8-bit sub-fields of 1) [Base] Class code, 2) Subclass code, and 3) Programming IF code. This register layout is in compliance with the PCI-SIG specification as described in section 7.5.1.1.6 of the PCIe Base Specification version 4.0r1.0.

    Therefore, the user must set the three 8-bit sub-fields accordingly, and the Class Code readout value in implemented hardware will be the combined 24-bit value of these three 8-bit sub-fields.

    Resolution

    Not applicable.

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