For an example in the code below, Quartus® Standard will have issues with RAM inference because of /*synthesis preserve*/
module mem
#(parameter DATA_WIDTH=8, parameter ADDR_WIDTH=6) (
input [(DATA_WIDTH-1):0] data,
input [(ADDR_WIDTH-1):0] read_addr, write_addr,
input we, clk,
output [(DATA_WIDTH-1):0] q,
output reg [3:0] state = 0/*synthesis preserve*/
);
simple_dual_port_ram_single_clock simple_dual_port_ram_single_clock_inst (
.data (data),
.read_addr (read_addr),
.write_addr (write_addr),
.we (we),
.clk (clk),
.q (q)
);
The issue is caused by a known limitation where any preserve in a module declaration is applied to the whole module when using Verilog 95 style. To fix this, use Verilog 2001 attribute style. Namely:
replace:
output reg [3:0] state = 0/*synthesis preserve*/
with:
(* preserve *) output reg [3:0] state = 0
This issue is not present in the Quartus® Pro version of the software. For Quartus® Standard versions, please use the workaround.