In the Quartus® Prime software, you may see the following fitter error message when compiling designs targetting Arria® 10 devices
Error(14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 pin(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error(175020): The Fitter cannot place logic pin in region (x, y) to (x, y), to which it is constrained, because there are no valid locations in the region for logic of this type.
Info(14596): Information about the failing component(s):
Info(175028): The pin name(s): <pin name>
Error(16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below:
Error(175005): Could not find a location with: OCT_CAL_BLOCK_ID of [n] (1 location affected)
Info(175029): <Pin number>
Info(175015): The I/O pad <pin name> is constrained to the location <Pin number> due to: User Location Constraints (<Pin number>)
Info(14709): The constrained I/O pad is contained within this pin
This may occur if the pin is in a 3V I/O Bank. 3V I/O Banks only support OCT without calibration.
For details on which banks are 3V I/O and which are LVDS, consult the Arria 10 Core Fabric and General Purpose I/Os Handbook, section 5.4.1
To avoid this error, move the pin to an LVDS Bank or use OCT without calibration.