Article ID: 000080372 Content Type: Troubleshooting Last Reviewed: 12/23/2022

Why do I get a warning about dedicated routing when using PLLs on Intel® MAX® 10 FPGA?

Environment

  • Intel® Quartus® Prime Standard Edition
  • PLL Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    The following warning is observed if the C0 output of the PLL block is not directly connected to the dedicated PLL output pins.

    Warning (15064): PLL "pll:pll50Mhz_int0|altpll:altpll_component|pll_altpll:auto_generated|pll1" output port feeds output pin via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance.

    Intel® MAX® 10 FPGA has dedicated PLL output pins, which can be directly connected to the C0 output of the PLL block. This connection ensures jitter performance is not impacted since it does not go through GCLK and is not affected by another part of the design. 

     

    Resolution

    To work around this warning, connect the C0 output of the PLL block directly to dedicated PLL output pins. Alternatively, you may ignore the warning if the reduction in jitter performance is not a concern.

     

    Related Products

    This article applies to 1 products

    Intel® MAX® 10 FPGAs

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