Article ID: 000080371 Content Type: Troubleshooting Last Reviewed: 01/11/2023

Why do I see Recovery timing violations from usr_rst_r to iopll_mac_clk in Intel® Agilex™ devices when using PAM4 variants of the Interlaken IP Core (2nd Generation) Intel® FPGA IP?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Interlaken (2nd Generation) Intel® FPGA IP
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    Critical Issue

    Description

    Due to a problem with the PAM4 implementation of the Interlaken IP Core (2nd Generation) Intel® FPGA IP, Recovery time timing closure violations may be seen from usr_rst_r to iopll_mac_clk in Intel® Agilex™ devices in Intel® Quartus® Prime Pro Edition v19.2 software. This problem is due to a modeling issue that incorrectly assumes usr_rst_r to synchronize with the IOPLL Reference Clock. The IOPLL User Guide states that the reset port is asynchronous to the reference clock.

     

     

    Resolution

    The recovery timing failure from usr_rst_r to iopll_mac_clk is false and can be safely ignored.

    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.

    Related Products

    This article applies to 2 products

    Intel® Agilex™ 7 FPGAs and SoC FPGAs F-Series
    Intel® Agilex™ 7 FPGAs and SoC FPGAs

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