Article ID: 000080368 Content Type: Troubleshooting Last Reviewed: 12/18/2019

Why does Intel® Stratix ® 10 Avalon®-ST Interface for PCI Express* IP show BAR size of 7 bits is supported?

Environment

  • Intel® Stratix® 10 FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • Avalon-ST Intel® Stratix® 10 Hard IP for PCI Express
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to incorrect rule check in the IP GUI, Intel® Stratix ® 10 Avalon®-ST Interface for PCI Express* IP for Intel® Quartus® Prime Pro 19.3 and
    earlier allows minimum BAR size of 7 bits to be selected. However, this selection will still show FPGA advertising 8 bits of BAR size.

    The minimum BAR size supported is 8 bits. 

    Resolution

    This problem is fixed in Intel® Quartus® Prime Pro software version 19.4.

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