Article ID: 000080367 Content Type: Troubleshooting Last Reviewed: 06/24/2019

Why do I get error "Unknown uid = xhip_block_1_1" when executing the a10_disableiei.tcl script to disable electrical idle inference for the Intel® Arria® 10 and Intel® Cyclone® 10 GX PCI-SIG Compliance Base Board (CBB) design?

Environment

  • Intel® Cyclone® 10 GX FPGA
  • Intel® Arria® 10 FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • Intel® Arria® 10 Cyclone® 10 Hard IP for PCI Express
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    The a10_disableiei.tcl script disables electrical idle inference for all 4 PCIe* Hard IPs of the Intel® Arria® 10.  Therefore, for Intel® Arria® 10 and Intel® Cyclone® 10 GX that have less than 4 PCIe* Hard IPs, executing the script will return this error.

    Internal Error: Sub-system: ASM2, File: /quartus/comp/asm2/asm2_state.cpp, Line: 1469

    Unknown uid = xhip_block_1_1

    Resolution

    To work around this problem, comment out the unavailble PCIe* Hard IPs in the a10_disableiei.tcl script.

    For example,  the 10AX115N1F40I1LP device uses only has 2 PCIe* Hard IPs not 4. Therefore, the 2 unavailable Hard IPs, xhip_block_1_1 and xhip_block_3_1, should be commented out. 

    xhip_block_1_0 = Bottom Left Location

    xhip_block_1_1 = Top Left Location

    xhip_block_3_0 = Bottom Right Location

    xhip_block_3_1 = Top Right Location

    Disclaimer

    1

    All postings and use of the content on this site are subject to Intel.com Terms of Use.