Internal Error: Sub-system: VRFX, File: /quartus/synth/vrfx/verific/vhdl/vhdlvalue_elab.cpp, Line: 6821

Due to a problem in the Quartus® II software, you may see this internal error if your VHDL code infers a dual-clock mixed-width dual-port memory with the process for the wider port placed before the process for the narrower port.

For example:

portA_p : PROCESS (clk)
BEGIN
IF (rising_edge(clk)) THEN
 IF we_a = '1' THEN
  -- Write access
  ram(addr_a / 2)(addr_a mod 2) := data_a;
  -- Read during write on the same port returns NEW data
  q_a <= data_a;
 ELSE
  -- Read returns OLD data
  q_a <= ram(addr_a / 2)(addr_a mod 2);
 END IF;
END IF;
END PROCESS portA_p;

portB_p : PROCESS (clk)
BEGIN
IF (rising_edge(clk)) THEN
 IF we_b = '1' THEN
  ram(addr_b) := data_b;
  -- Read during write on the same port returns NEW data
  q_b <= data_b;
 ELSE
  -- Read returns OLD data
  q_b <= ram(addr_b);
 END IF;
END IF;
END PROCESS portB_p;

To work around this problem, reverse the order of the processes so that the process for the wider port appears first.

This problem is scheduled to fixed in a future release of the Quartus II software.