Article ID: 000080313 Content Type: Troubleshooting Last Reviewed: 10/15/2012

Why am I not able to place more than two independent ALTLVDS interfaces in one I/O sub-bank in Arria V devices?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Arria®V devices support up to two independent ALTLVDS interfaces in each sub-bank. For example you can place two ALTLVDS interfaces in bank 8A driven by two different PLLs provided the LVDS channels are not interleaved.

If you violate this limitation, you will receive an error message during project compilation.

Related Products

This article applies to 5 products

Arria® V GZ FPGA
Arria® V ST SoC FPGA
Arria® V SX SoC FPGA
Arria® V GT FPGA
Arria® V GX FPGA

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