Why is my Fast Input Register, Fast Output Register or Fast Output Enable Register assignment ignored when enabling the SignalTap II Logic Analyzer in my design?

When the SignalTap™ II Logic Analyzer is included in a design, register control signals may be promoted to global nets by the Quartus® II software. Registers with control signals on global nets cannot be packed into the I/O element. If a register with a Fast Input Register, Fast Output Register or Fast Output Enable Register assignment cannot be packed into the I/O element, the following warning message is generated:

Warning: Ignoring invalid fast I/O register assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.

To work around this problem, prevent the control signal from being promoted to a global signal by following these steps:

1. Open the Assignment Editor from the Assignments menu.
2. Create a new assignment by clicking <<new>> on the Filter bar.
3. Enter the name of the control signal by typing it in the To field or by double-clicking and using the Node Finder tool.
4. Select Global Signal in the Assignment Name field.
5. Select Off in the Value field.