Article ID: 000080293 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why do PLL reconfiguration signals toggle after local_init_done goes high in DDR/DDR2 high performance controller simulation?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

The PLL will reconfigure after entering the user mode which is indicated by local_init_done signal because mimic path calibration sequence of the core runs after going into the user mode to take into account voltage and temperature changes.

The mimic path will  re-calibrate every 200ms, or if voltage and  temperature varies during the user mode.

Refer to "Mimic Path" section of External DDR Memory PHY interface Megafunction User Guide (Altmemphy) (PDF)  for more details.

Related Products

This article applies to 2 products

Stratix® III FPGAs
Stratix® II FPGAs

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