Article ID: 000080291 Content Type: Troubleshooting Last Reviewed: 11/07/2014

Is there a known problem with the self-reset feature when using the Altera PLL IP in Stratix V, Arria V or Cyclone V devices?

Environment

    Quartus® II Subscription Edition
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Due to a known problem in Quartus® II software version 13.1, the self reset feature in the Altera® PLL IP may not work properly when the PLL loses lock in Stratix® V, Arria® V or Cyclone® V devices. 

 

Resolution This problem is fixed in Quartus II version 13.1 update 3.

Related Products

This article applies to 15 products

Cyclone® V SX SoC FPGA
Cyclone® V GT FPGA
Stratix® V GX FPGA
Cyclone® V GX FPGA
Stratix® V GT FPGA
Arria® V GZ FPGA
Stratix® V GS FPGA
Arria® V SX SoC FPGA
Cyclone® V ST SoC FPGA
Arria® V ST SoC FPGA
Arria® V GX FPGA
Arria® V GT FPGA
Cyclone® V E FPGA
Stratix® V E FPGA
Cyclone® V SE SoC FPGA

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