PIPE simulations of PCI Express in Stratix IV devices fail. A descrepancy between
the definition of
eidle_infer_sel signal in the PCI Express IP core
and in altpcie_hip_pipen1b_qsys causes the failure.
eidle_infer_sel is defined as a 12-bit vector in the IP core and 24
bits in altpcie_hip_pipen1b_qsys.
The workaround is to simulate in serial mode.