Why does the time interval for four active windows during RTL simulation not match the tFAW setting in the Intel® Arria® 10 FPGA DDR4 IP GUI?

Due to a rounding problem with the Intel® Arria® 10 FPGA DDR4 IP in the Quartus® II software version 14.1, the DDR4 four active windows time seen during RTL simulation might not match the tFAW setting in the DDR4 IP GUI, which will result in lower efficiency.

An example of when you might see this is with the IP Memory Clock Frequency parameter set to 1066.667 MHz.

As a workaround, modify the memory clock frequency. In the example above, change the Memory Clock Frequency from 1066.667 MHz to 1066.666 MHz and then re-generate the DDR4 IP.

This problem is scheduled to be fixed in a future version of the Quartus II software.