Article ID: 000080267 Content Type: Error Messages Last Reviewed: 06/09/2022

Error: **_emif_a10_hps_0: PLL reference clock frequency of 25.0 MHz is invalid. Please select another value, or enable the option to use the recommended value.

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

The error message appears because the PLL reference clock setting does not meet the I/O PLL requirements. For further details, refer to the erratum New Restrictions on I/O PLL Configuration Imposed in 15.1 for Arria 10 EMIF IP 

 

Resolution

You will need to apply a higher PLL reference clock frequency setting to meet the I/O PLL performance.

Related Products

This article applies to 3 products

Intel® Arria® 10 GT FPGA
Intel® Arria® 10 GX FPGA
Intel® Arria® 10 SX SoC FPGA

Disclaimer

1

All postings and use of the content on this site are subject to Intel.com Terms of Use.