Article ID: 000080234 Content Type: Troubleshooting Last Reviewed: 09/26/2013

When accessing the ETH_RX_DATA register, why does the CPU interface of the CPRI MegaCore function stop resopnding?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

When the ETH_RX_DATA register is accessed on the CPU interface, the CPRI MegaCore® function waits until a frame of Ethernet data is received on the Fast C & M interface.  If you have not setup the Fast C & M interface or the link partner is not transmitting, then the CPU interface waits indefinitely and the cpu_waitrequest signal remains asserted.

Altera® recommends that you read the CPRI_CM_STATUS register to ensure that an RX Fast C & M channel has been initialized as indicated by the rx_fast_dm_ptr_valid bit prior to accessing the Ethernet Registers.

Related Products

This article applies to 3 products

Stratix® V FPGAs
Cyclone® V FPGAs and SoC FPGAs
Arria® V FPGAs and SoC FPGAs