Article ID: 000080202 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Are there any guidelines on when to assert DPA reset in Soft-CDR mode?

Environment

  • Reset
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    There are no guidelines from Altera® about when to reset the DPA when using Soft-CDR in Stratix® III and Stratix IV devices. The rx_reset resets the DPA circuitry and the FIFO contents. However, rx_reset may be asserted when link retraining is needed for the DPA to lock to a new phase.

    In Soft-CDR mode, the rx_reset does not need to be asserted as the DPA continuously locks to a new phase depending on ppm differences between the reference clock and the incoming data.

    Related Products

    This article applies to 3 products

    Stratix® III FPGAs
    Stratix® IV GX FPGA
    Stratix® IV E FPGA

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