Article ID: 000080183 Content Type: Product Information & Documentation Last Reviewed: 12/23/2014

How do I ensure low skew between the two pins that make up an emulated LVDS output on MAX V devices?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

MAX® V devices support emulated LVDS outputs using the LVDS_E_3R I/O standard.  If the LVDS_E_3R I/O standard is applied to an output, the Quartus® II software will infer an inverted output to make up the differential pair.  The inferred differential pair will not have constrained routing and may have very high skew between the two output pins.

Resolution

To ensure that the Quartus II software uses low skew routing between the two parts of the differential pair, the output must be an output from a maxv_io WYSIWYG.

The ALTLVDS_TX megafunction includes the maxv_io WYSIWYG so any outputs from an ALTLVDS_TX megafunction will automatically use the correct routing.

The maxv_io is contained in the device libraries as follows:
Verilog: <quartus install directory>/eda/sim_lib/maxv_atoms.v
VHDL: <quartus install directory>/eda/sim_lib/maxv_components.vhd

Related Products

This article applies to 1 products

MAX® V CPLDs

Disclaimer

1

All postings and use of the content on this site are subject to Intel.com Terms of Use.