PLL dynamic reconfiguration reset does not restore the originally programmed PLL settings in the Arria 10 device

For the Arria V, Cyclone V, and Stratix V devices, you can use the Altera phase-locked loop (PLL) reconfiguration IP to dynamically reconfigure the settings of the device fractional PLL (fPLL). Asserting the mgmt_reset signal on the PLL reconfiguration IP restores the fPLL to its original SRAM Object File (.sof) settings. This restore function is for V-series devices only; it does not exist when reconfiguring the I/O PLL or fPLL in the Arria 10 device.

You can use the PLL reconfiguration IP to reconfigure the I/O PLLs settings, but asserting the mgmt_reset signal on the IP will not restore the original .sof settings of the I/O PLL. Asserting the reset signal clears the command FIFO buffer in the IP. If you assert the I/O PLL reset, the I/O PLL will lose and regain lock, but the new settings will be preserved.

For the Arria 10 device, the high-speed serial interface (HSSI) fPLL has an Avalon Memory-Mapped (Avalon-MM) interface for reconfiguration. The Avalon-MM interface is raw to allow you to dynamically change settings at run time. Your new fPLL settings are preserved when asserting the transceiver dynamic reconfiguration reset, the PLL reset, or both resets.

For fPLL:

• The HSSI fPLL IP has an option to dump configuration settings into a Memory Initialization File (.mif), a System Verilog Design File (.sv) or C header file. When reconfiguring your Arria 10 device from a first configuration to a second configuration, you must generate two variations of the HSSI fPLL IP to generate the .mif, .sv, or C header file. You can use one of these files to stream in the new settings to change the fPLL settings from your first configuration to your second configuration.

For I/O PLL:

• The I/O PLL IP has an option to dump configuration settings into a .mif. Multiple PLL configurations can be combined together into a single .mif and can be loaded into the PLL reconfiguration IP. You can use this file to stream in the new settings to change the I/O PLL settings between multiple configurations.

Two fPLL example designs are provided to help you with the reconfiguration. The first example demonstrates .sv file streaming using the configuration array in the Native PHY IP core. The second example demonstrates how to modify the HSSI fPLL couple counter settings through the Avalon-MM interface without having to stream the entire configuration.

Please contact Altera if you require more information.