Article ID: 000080163 Content Type: Product Information & Documentation Last Reviewed: 09/11/2012

How do I use the source-synchronous compensation mode for a multi-pin bus?



Beginning with the Quartus® II software version 7.2, the PLL source-synchronous compensation mode can compensate multiple pad-to-input-register paths, such as a data bus. Use the "PLL Compensation" assignment in the Assignment Editor to select which input pins are used as the PLL compensation targets. You can include your entire data bus, for example, if the input registers are driven by the same output of a source-synchronous compensated PLL. To be properly compensated, all of the pins should be on the same side of the device. The PLL compensates for the input pin with the longest corresponding pad-to-register delay of all input pins in the compensated bus.

If you do not choose compensation targets, the Quartus II software automatically selects all the pins driven by the compensated output of the PLL as the compensation targets.

In the Quartus II software versions 7.1 SP1 and earlier, the PLL source-synchronous compensation mode can compensate only one input path to an IOE register. Refer to the solution in the Related Solutions section for more information about the issue in the Quartus II software versions 7.1 SP1 and earlier.

Related Products

This article applies to 6 products

Cyclone® III FPGAs
Cyclone® II FPGA
Arria® GX FPGA
Stratix® II GX FPGA
Stratix® II FPGAs
Stratix® III FPGAs



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