Article ID: 000080160 Content Type: Troubleshooting Last Reviewed: 09/23/2012

Why will the Altera 40G and 100G MACs produce the Error message,"tx padding state machine is corrupt" during simulation?

Environment

  • Quartus® II Subscription Edition
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    Description

    The Altera® 40G and 100G MACs will display the error message,"tx padding state machine is corrupt" if the connected Avalon® interface was not driven as expected. The following rules must be followed:

    1. Packets must start with an SOP which will also be the MSB of the data, and end with an EOP. No additional SOPs or EOPs are allowed within a packet.
    2. Their must be a minimum of two clock cycles between packets.
    3. tx_valid must remain high during packet transmission.

    Related Products

    This article applies to 2 products

    Stratix® IV GT FPGA
    Stratix® V GX FPGA

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