Why does my SCFIFO almost_empty signal remain stuck at '1' in simulation?

Due to a problem in the SCFIFO simulation model in the Quartus® II software, you may see the almost_empty signal be permenently asserted in simulation if you perform a read and a write while the SCFIFO is empty. This problem only occurs if you have disabled underflow circuitry protection and set the almost empty value to 2.

This problem only affects simulation, hardware performance is unaffected.

To work around this issue, perform one of the following actions:

• Do not perform a read and write in simulation while the SCFIFO is empty
• Set the almost empty value to something other than 2
• Enable underflow circuitry protection

This problem is scheduled to be fixed in a future release of the Quartus II software.