Article ID: 000080120 Content Type: Error Messages Last Reviewed: 10/29/2015

Error nofile(37) in protected region

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description You may experience the above error while simulating a VHDL-based DDR3 UniPHY memory controller design with ModelSim. When the DDR3 memory controller is generated in VHDL, all Verilog and SystemVerilog submodules are encrypted to allow simulation with a single-language simulator. If an error occurs in the encrypted fileset, a cryptic message like the one above will be generated.
Resolution

Make sure the DDR3 files are being compiled in the order specified in the msim_setup.tcl file located in the <variation_name>_sim directory. Any files compiled out-of-order may result in the above error.

 

Related Products

This article applies to 27 products

Cyclone® V GT FPGA
Cyclone® III FPGAs
Stratix® V GX FPGA
Cyclone® IV GX FPGA
Cyclone® V GX FPGA
Arria® V GZ FPGA
Stratix® V GS FPGA
Stratix® II GX FPGA
Stratix® II FPGAs
Arria® V GX FPGA
Stratix® V GT FPGA
Arria® V GT FPGA
Stratix® III FPGAs
Stratix® IV GX FPGA
Arria® II GX FPGA
Arria® II GZ FPGA
Stratix® IV GT FPGA
Cyclone® V E FPGA
Cyclone® V SX SoC FPGA
Stratix® V E FPGA
Cyclone® V ST SoC FPGA
Cyclone® V SE SoC FPGA
Cyclone® IV E FPGA
Arria® V SX SoC FPGA
Arria® V ST SoC FPGA
Cyclone® III LS FPGA
Stratix® IV E FPGA

1

Need more help?

Contact support

Disclaimer

1

All postings and use of the content on this site are subject to Intel.com Terms of Use.