Article ID: 000080099 Content Type: Troubleshooting Last Reviewed: 08/27/2013

Is there an issue when merging PLLs which use cascaded post-scale counters in Stratix III and Stratix IV devices in the Quartus II software version 11.0SP1 and earlier?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

For Stratix® III and Stratix IV devices, the Quartus® II software versions 11.0 SP1 and earlier may generate the wrong low frequency output clocks if at least one of the PLLs uses cascaded post-scale counters to achieve low output clock frequencies, and that PLL is merged with another in your design.

The Quartus II software can merge PLLs when two (or more) ALTPLL instances in your design can be combined to one PLL resource.  For example, if two ALTPLL megafunctions have the same reference clock, the same reset signal, and each have output clocks that can be produced by a single PLL, then they will be merged into the same resource.

In the Quartus II software versions 11.0SP1 and earlier, the merging function does not properly implement the cascaded counter.  The PLL usage report will show the intended clock frequency has been implemented, and timing analysis will be performed at the intended clock rate, but the clock output may not have the desired output frequency in the device.

To work around this problem, turn off "Auto Merge PLLs" for your project.  This option can be found in the Assignments menu - Settings - Fitter Settings - More Fitter Settings.

 

Related Products

This article applies to 4 products

Stratix® III FPGAs
Stratix® IV GT FPGA
Stratix® IV E FPGA
Stratix® IV GX FPGA

Disclaimer

1

All postings and use of the content on this site are subject to Intel.com Terms of Use.