How do the shift operators in Verilog HDL get synthesized in the MAX PLUS® II software?

reg [3:0] in;
                  output [3:0] shfta;

assign shfta = {in

In this case, since shfta is four bits wide, the value of {in<<2} is truncated to the least 4 bits. If in = 4'b0100, then shfta = 4'b0000. The two most significant bits of the 6-bit shifted value are lost.

In the following code, a 6-bit shifted value is preserved and shfta is assigned the correct value. If in=4'b0100, then shfta = 6'b010000.

              reg [3:0] in;
             output [5:0] shfta;

             assign shfta = {in<<2};

The MAX PLUS II software infers the right size for the shift operation depending on the size of the variable on the left hand side of the assignment statement. Consider the following code:

             reg [3:0] in;
             output [7:0] shfta;

             assign shfta = {in<<2}   7'h10;

Since shfta is eight bits wide, {in<<2} is assigned eight bits. The same rules apply for the >> operator. However, due to the nature of the >> operator, the results would not be affected by the width of the shift operator implementation. For example, if in =4'b1000, then {in>>2} is 4'b0010. The left side of the shifted data is padded with zeros. Here the most significant bits are not lost. Instead, the least significant bits are lost due to the shift operation independent of the width of the shift operator implementation.