DisplayPort Intel® FPGA IP Pixel Clock Recovery Module Doesn't Work with Certain Resolutions

The pixel clock recovery module used in the DisplayPort Intel® FPGA IP pass-through designs fails to recover pixel clocks of certain resolutions, and the fPLL will lose the lock. This is due to the following:

1. The resolutions that fail result in a Mvid value, an integer submultiple of Nvid. For example:

    Bitrate = 270 MHz (HBR)

    Expected Pixel clk= 135 MHz

    Mvid= \'h4000

    Nvid= \'h8000

OR

    Bitrate = 540 MHz (HBR2)

    Expected Pixel clk= 539.98 MHz

    Mvid= \'h7FFF (near Nvid)

    Nvid= \'h8000

2. The fractional PLL MFRAC value is out of the recommended range, which must be between the 0.05 and 0.95 range. Note that the MFRAC value is derived from the K-counter value. Refer to AN661: Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig IP Cores for more information.

Option 1:

Avoid using pixel clock frequency that results in a Mvid value with integer submultiple(or near) of Nvid value and MFRAC value that exceeds the recommended range. To identify the MFRAC value:

1.  SignalTap the K counter value.

            K-counter location:             bitec_clkrec:bitec_clkrec_i|bitec_fpll_cntrl:bitec_fpll_cntrl_i|bitec_fpll_reconf:vseries_reconfig.clkrec_pll_reconf_i|altera_pll_reconfig_top:bitec_fpll_reconf_inst|altera_pll_reconfig_core:NM28_reconfig.reconfig_core.altera_pll_reconfig_core_inst0|usr_k_value[31..0]

2. Calculate the MFRAC value.

           MFRAC = K(in decimal)/2^32 (in decimal is  4,294,967,296).    

Option 2:

Migrate your design to Intel® Stratix® 10 device, Intel® Arria® 10 device, or  Intel® Cyclone® 10 GX devices from  Arria® V device, Cyclone® V device, or Stratix® V device design.